Recently, as a next generation NVRAM (Nonvolatile Random Access Memory) capable of performing a high-speed operation to replace a flash memory, various devices such as a FeRAM (Ferroelectric RAM), an MRAM (Magnetic RAM), and an OUM (Ovonic Unified Memory) have been proposed and they are being developed competitively in view of implementing high performance, high reliability, low cost and process consistency.
In addition, based on these existing techniques, a method of changing electric resistance reversibly by applying a voltage pulse to the perovskite material known for a super colossal magnetoresistance effect is disclosed by Shangquing Liu, Alex Ignatiev et al. in University of Houston, in the following Patent Document 1 and Non-patent Document 1. This is extremely innovative because resistance change over several digits can be implemented at a room temperature without applying an electric field while using the perovskite material known for the super colossal magnetoresistance effect. A resistance nonvolatile RRAM (Resistance Random Access Memory: RRAM is a registered trademark of Sharp Corporation) using a variable resistance element and employing this phenomenon is extremely low in power consumption because it does not need a magnetic field at all unlike the MRAM and easy to be miniaturized and highly integrated and has a considerably large dynamic range of the resistance change as compared with the MRAM, so that it has excellent characteristics such that multilevel storage can be implemented. The basic structure in an actual device is considerably simple such that a lower electrode material, a perovskite-type metal oxide, and an upper electrode material are laminated in this order on a substrate in the vertical direction. In addition, according to the element structure illustrated in Patent Document 1, the lower electrode material is yttrium-barium-copper oxide YBa2Cu3O7 (YBCO) film deposited on a single-crystal substrate of lanthanum-aluminum oxide LaAlO3 (LAO), the Perovskite-type metal oxide is a crystalline praseodymium-calcium-manganese oxide Pr1-xCaxMnO3 (PCMO) film, and the upper electrode material is an Ag film deposited by sputtering. According to the action of the memory element, it is reported that the resistance can be reversibly changed by applying positive and negative voltage pulse of 51 volts between the upper and lower electrodes. The novel nonvolatile semiconductor memory device is implemented by reading the resistance value in this reversible resistance changing action (referred to as the “switching action” occasionally hereinafter).
A nonvolatile semiconductor memory device is constituted such that a memory cell array in which memory cells comprising a variable resistance element consisting of the PCMO film and the like and storing information by the change of the electric resistance of the variable resistance element are arranged in a row direction and column direction like a matrix is formed, and circuits for controlling data programming, erasing and reading for each memory cell in the memory cell array are disposed in the periphery of the memory cell array.
As the constitution of the memory cell comprising the variable resistance element, there is a case where each memory cell comprises a series circuit in which a variable resistance element and a selection transistor are connected in series, and a case where each memory cell comprises only a variable resistance element. The former memory cell is referred to as the 1T/1R type memory cell and the latter memory cell is referred to as the 1R type memory cell. In addition, the memory cell array comprising the 1R type memory cells is referred to as the cross-point type memory cell array.
A constitution example in which the cross-point type memory cell array is formed with the 1R type memory cells to provide a large capacity nonvolatile semiconductor memory device will be described with reference to the drawings hereinafter.
As shown in FIG. 1, a memory cell 2 comprises a variable resistance element 1 only and a cross-point type memory cell array 3 is constituted by arranging the 1R type memory cells 2 like a matrix, and this is the same constitution as disclosed in the following patent document 2. More specifically the memory cell array 3 is constituted such that (m×n) memory cells 2 are disposed at intersections of m (BL1 to BLm) bit lines extending in the column direction and n (WL1 to WLn) word lines extending in the row direction. According to each memory cell 2, the upper electrode of the variable resistance element 1 is connected to the word line, and the lower electrode of the variable resistance element 1 is connected to the bit line. In addition, the relation between the upper electrode and the lower electrode of the variable resistance element 1 may be reversed such that the lower electrode of the variable resistance element 1 is connected to the word line and the upper electrode of the variable resistance element 1 is connected to the bit line.
FIG. 2 shows one constitution example of a nonvolatile semiconductor memory device comprising the cross-point type memory cell array 3. A specific memory cell in the memory cell array 3 corresponding to an address inputted from an address line 9 to a control circuit 6 is selected by a bit line decoder 4 and a word line decoder 5 and each memory action such as data programming, erasing and reading is performed for the memory cell, so that data is stored in the selected memory cell and read from it. The data is inputted or outputted to and from an external device (not shown) through a data line 10.
The word line decoder 5 selects the word line of the memory cell array 3 according to a signal inputted to the address line 9. The bit line decoder 4 selects the bit line of the memory cell array 3 according to an address signal inputted to the address line 9. The control circuit 6 controls each memory action such as programming, erasing and reading for the memory cell array 3.
The control circuit 6 controls the word line decoder 5, the bit line decoder 4, a voltage switch circuit 7, and the programming, erasing and reading action of the memory cell array 3, based on the address signal inputted from the address line 9, a data input (at the time of programming) inputted from the data line 10, and a control input signal inputted from a control signal line 11. In the example shown in FIG. 2, the control circuit 6 is provided with a function as a general address buffer circuit, data input/output buffer circuit, and control input buffer circuit though they are not shown.
The voltage switch circuit 7 switches each voltage of the word line and bit line required for the reading action, programming action and erasing action of the memory cell array 3 according to an action mode and supplies it to the memory cell array 3. Here, reference character Vcc designates a power supply voltage of the nonvolatile semiconductor memory device of the present invention, reference character Vss designates the ground voltage, reference character Vr designates a reading voltage, reference character Vp designates a programming supply voltage (programming voltage) and reference character Ve designates an erasing supply voltage (erasing voltage is −Ve). In addition, the data reading is carried out from the memory cell array 3 through the bit line decoder 4 and the reading circuit 8. The reading circuit 8 determines the state of the data and transfers its result to the control circuit 6 to be outputted to the data line 10.
In the memory cell array comprising the 1T/1R type memory cells, when a memory cell for which the data reading, programming and erasing is performed is selected, a predetermined bias voltage is applied to a selected word line and a selected bit line to turn on the selection transistor in the selected memory cell connected to both selected word line and selected bit line, so that a reading and programming/erasing current flows in only the variable resistance element in the selected memory cell.
Meanwhile, according to the memory cell array 3 comprising the 1R type memory cells 2, when a memory cell for which the data reading is performed is selected, since the same bias voltage is applied also to memory cells connected to the word line and bit line shared with the memory cell to be read, the reading current flows in other memory cells. The reading current flowing in the selected memory cells selected by the row or column is detected as the reading current of the memory cell to be read by column selection or row selection. According to the memory cell array 3 comprising the 1R type memory cells 2, although the reading current also flows in the memory cells other than the memory cell to be read, it has advantages that its memory cell structure is simple and a memory cell area and memory cell array area are small.
FIGS. 1 and 3 show a conventional example of a process in which a voltage is applied to each part at the time of data reading action in the memory cell array 3 comprising the 1R type memory cells 2. When the data of the selected memory cell is read, the selected word line connected to the selected memory cell is kept at the ground potential Vss and a reading voltage Vr is applied to unselected word lines and all the bit lines during a reading period Tr. During the reading period Tr, since the voltage difference of the reading voltage Vr is generated between the selected word line and all the bit lines, a reading current corresponding to its electric resistance, that is, its memory state flows in the variable resistance element of the selected memory cell, so that the data stored in the selected memory cell can be read. In this case, since the reading current corresponding to the memory state of the selected memory cell connected to the selected word line flows in each bit line, when the reading current flowing in a certain selected bit line is selectively read on the bit line side, the data in the specific selected memory cell can be read. Here, the relation of the bit line and the word line may be switched such that the reading current flowing in each word line is selectively read on the word line side.
FIGS. 4 and 5 show a conventional example of a process in which a voltage is applied to each part in the memory cell array 3 comprising the 1R type memory cells 2 at the time of data programming action. In addition, FIGS. 6 and 7 show a conventional example of a process in which a voltage is applied to each part in the memory cell array 3 comprising the 1R type memory cells 2 at the time of data erasing action. In addition, the following non-patent document 2 discloses a specific voltage bias condition applied to the word line and bit line at the time of data reading action and data programming action for the cross-point type memory cell array.
As shown in FIGS. 4 and 5, when data is programmed in a selected memory cell M0, while the selected word line connected to the selected memory cell is kept at the ground potential Vss, a programming blocking voltage Vp/2 is applied to the unselected word lines and unselected bit lines and the programming voltage Vp is applied to the selected bit line in the programming period Tp.
In the programming period Tp, the voltage difference of the programming voltage Vp is generated between the selected bit line and the selected word line, so that the resistance of the variable resistance element of the selected memory cell is changed. In addition, at the time of programming action of the selected memory cell, the voltage Vp/2 that is the half of the programming voltage Vp is applied to each variable resistance element of the first unselected memory cells M1 connected to the word line shared with the selected memory cell, and the second unselected memory cells M2 connected to the bit line shared with the selected memory cell for the programming period Tp.
When data is erased from the selected memory cell M0, the voltage having the opposite polarity to that in the programming is applied to the variable resistance element of the selected memory cell M0. As shown in FIGS. 6 and 7, while the selected bit line connected to the selected memory cell is kept at the ground potential Vss, an erasing blocking voltage (−Ve/2) is applied to the unselected bit lines and the unselected word lines and the erasing voltage (−Ve) is applied to the selected word line in the erasing period Te.
In the erasing period Te, the voltage difference of the erasing voltage Ve is generated between the selected bit line and the selected word line, so that the resistance of the variable resistance element of the selected memory cell is changed. In addition, at the time of erasing action of the selected memory cell, the voltage (−Ve/2) that is the half of the erasing voltage (−Ve) is applied to each variable resistance element of the first unselected memory cells M1 connected to the word line shared with the selected memory cell, and the second unselected memory cells M2 connected to the bit line shared with the selected memory cell for the erasing period Te.
Here, the relation between the bit line and the word line may be exchanged in the programming action and the erasing action.
The variable resistance element constituting the 1R type memory cell includes a phase-change memory element in which a resistance value is changed by the change in crystalline/amorphous state of chalcogenide compound, an MRAM element using a resistance change by a tunnel magnetic resistance effect, a memory element of a polymer ferroelectric RAM (PFRAM) in which a resistance element is formed of a conductive polymer, a RRAM element causing a resistance change by an electric pulse application and the like.    Patent document 1 U.S. Pat. No. 6,204,139    Patent document 2 Japanese Unexamined Patent Publication No. 2002-8369    Non-patent document 1: Liu, S. Q. et al. “Electric-pulse-induced reversible Resistance change effect in magnetoresistive films”, Applied Physics Letter, Vol. 76, pp. 2749-2751, in 2000.    Non-patent document 2: Y. Chen et al. “An Access-Transistor-Free (0T/1R) Non-Volatile Resistance Random Access Memory (RRAM) Using a Novel Threshold Switching, Self-Rectifying Chalcogenide Device”, IEDM Technical Digest, Session 37, in 2003.
When data programming or erasing is performed for the cross-point type memory cell array comprising the 1R type memory cell having the variable resistance element, a bias voltage is applied to the variable resistance element of the selected memory cell to change its resistance to perform the programming or erasing. In this case, the voltage that is the half of the programming voltage or erasing voltage is applied to each variable resistance element of the unselected memory cells connected to the bit line shared with the selected memory cell and the unselected memory cells connected to the word line shared with the selected memory cell. The voltage that is the half of the programming voltage or erasing voltage is generated when the programming blocking voltage or the erasing blocking voltage is applied to the unselected word lines and unselected bit lines so that the programming voltage or erasing voltage is not directly applied to the unselected memory cells in order to prevent programming or erasing in the unselected memory cells for which the programming or erasing is not to be performed. That is, in order to prevent programming or erasing in the unselected memory cells, a low voltage that is insufficient for the programming or erasing action is applied.
However, the inventors of this disclosure have found that in the case where the PCMO film (Pr1-xCaxMnO3) that is one of the Perovskite type metal oxide is used as the variable resistance element, when a voltage pulse having a voltage magnitude that is not more than the half of the programming voltage and the same polarity as the programming voltage is continuously applied to the variable resistance elements of the unselected memory cells, as the number of applications is increased, the resistance value of the variable resistance element is gradually changed. That is, it means that while the programming action or the erasing action is repeated in the cross-point type memory cell array unexpected error programming or error erasing is generated (this phenomenon is referred to as the “programming disturbance” or “erasing disturbance” hereinafter) in the unselected memory cells other than the memory cell in which the programming or erasing is performed.
FIG. 8 shows the behavior of the resistance change when five kinds of voltage pulses having different voltage magnitudes, voltage polarities, applying methods are applied to the variable resistance element whose initial state is in a high resistance state. As shown in FIG. 8, when a voltage pulse having a positive polarity (whose pulse width is 100 ns) is continuously applied to the upper electrode of the variable resistance element (shown by a curved line pointed by arrow A), the resistance value of the variable resistance element whose initial state was in the high resistance state is reduced as the number of pulse applications is increased. In addition, when a voltage pulse having a negative polarity (whose pulse width is 100 ns) is continuously applied (shown by a curved line pointed by arrow B), the resistance value of the variable resistance element whose initial state was in the high resistance state is increased as the number of pulse applications is increased. In addition, as for the voltage pulse having the negative polarity, although the resistance value tends to be increased as the number of pulse applications is increased, since the fact that the high resistance state further becomes high resistance state means that the difference from the low resistance state becomes great, this is no problem in view of characteristics. Meanwhile, the problem is that the resistance value is decreased when the voltage pulse having the positive polarity is applied. In FIG. 8, the curved line A designates the application of the voltage pulse having the positive polarity whose voltage magnitude is the half of the programming voltage, and the curved line B designates the application of the voltage pulse having the negative polarity whose voltage magnitude is the half of the programming voltage.
Here, the voltage pulse having the positive polarity means the state in which the reference ground voltage is applied to the lower electrode and a positive voltage pulse (having a voltage magnitude of 1V, for example) is applied to the upper electrode. In addition, the voltage pulse having the negative polarity means the state in which the reference ground voltage is applied to the upper electrode and a positive voltage pulse (having a voltage magnitude of 1V, for example) is applied to the lower electrode. Furthermore, the measuring condition of the resistance value shown in FIG. 8 has been calculated from a current value when the reference ground voltage is applied to the lower electrode and 0.5V is applied to the upper electrode. In addition, the horizontal axis in FIG. 8 designates the relative number of applications of the voltage pulse in a logarithmic manner.
FIG. 9 shows the behavior of the resistance change when six kinds of voltage pulses having different voltage magnitudes, voltage polarities, and application methods are applied to the variable resistance element whose initial state is in the low resistance state. In addition, the measuring condition of the resistance value shown in FIG. 9 has been calculated from the current value when the reference ground voltage is applied to the lower electrode and 0.5V is applied to the upper electrode. In addition, the horizontal axis in FIG. 9 designates the relative number of applications of the voltage pulse in a logarithmic manner. As shown in FIG. 9, it can be seen that when the initial state is the low resistance state, the resistance change is small as compared with the case where the initial state is the high resistance state. In FIG. 9, a curved line A designates the application of a voltage pulse having a positive polarity whose voltage magnitude is one fourth of the programming voltage, and a curved line B designates the application of a voltage pulse having a positive polarity whose voltage magnitude is the half of the programming voltage.
As a result, it has become clear that the programming disturbance phenomenon in which the resistance state is changed from the initial state in accordance with the number of applications is caused because the voltage pulse whose voltage magnitude is the half of the programming voltage or less and polarity is the same is applied to each variable resistance element of the unselected memory cells connected to the bit line shared with the selected memory cell, and the unselected memory cells connected to the word line shared with the selected memory cell during the programming period for the selected memory cell. Especially, since the programming disturbance phenomenon is obvious on the variable resistance element whose initial state is high resistance state, the problem that the resistance value of the variable resistance element is decreased and the resistance difference between the high resistance state and the low resistance state becomes small and its reading margin is lowered is raised. In addition, since the repeating frequency of the programming actions at the low voltage for the unselected memory cells is increased in the large capacity memory cell array having many word lines and bit lines, the disturbance is caused frequently, and as the worst case, the stored data is completely erased and it cannot be read. In addition, the same is true in the erasing action.
Especially, when the programming blocking voltage that is the half of the programming voltage or the erasing blocking voltage that is the half of the erasing voltage is applied to the unselected word lines and the unselected bit lines during the programming period or erasing period, since the voltage whose voltage magnitude is the half of the programming voltage or erasing voltage and polarity is the same is applied to each variable resistance element of the unselected memory cells connected to the bit line shared with the selected memory cell, and the unselected memory cells connected to the word line shared with the selected memory cell, the programming disturbance phenomenon becomes more obvious.
In addition, when two kinds of programming blocking voltages that are one third and two thirds of the programming voltage, or two kinds of erasing blocking voltages that are one third and two thirds of the erasing voltage are applied to each of the unselected word lines and unselected bit lines during the programming period or the erasing period, the voltage whose voltage magnitude is one third of the programming voltage or erasing voltage and polarity is the same is applied to each variable resistance element of the unselected memory cells connected to the bit line shared with the selected memory cell, and the unselected memory cells connected to the word line shared with the selected memory cell, and the voltage whose voltage magnitude is one third of the programming voltage or erasing voltage and polarity is opposite is applied to each variable resistance element of the unselected memory cells connected to the word lines and bit lines that are not connected to the selected memory cell. In this case, since the number of third unselected memory cells, to which the voltage having the opposite polarity is applied, is huge in the large capacity memory cell array having many word lines or bit lines, when the programming disturbance phenomenon or the erasing disturbance phenomenon due to the application of the voltage having the opposite polarity could be generated, care should be taken because the application number is large although the applied voltage is as low as one third of the programming voltage or erasing voltage as compared with the case the applied voltage is the half thereof. In addition, the polarity in programming and erasing is changed due to the material, film quality, composition, temperature, structure, programming/erasing time and the like of the variable resistance element in some cases.
One or more aspects of the present invention has been made in view of the above problems and it is an object of one or more aspects to provide a nonvolatile semiconductor memory device in which resistance change in the unselected memory cells due to the programming or erasing action for the cross-point type memory cell array comprising the variable resistance elements is prevented and the reading margin is large.